|
|
EECE2322: Fall 2023
Section 05:
Mon, Wed, & Thu 1:35pm - 2:40pm
Location: Shillman 315
Office Hours: Wed & Thu 9:00am - 10:00am
Course Syllabus |
|
|
|
Fall 2023
Course Description and Overview:This course offers a global perspective on the design of a full processor taking logic gates as the simplest building blocks. The course begins with the design of simple combinational and sequential circuits, continues with an introduction to the RISC-V instruction set architecture (ISA), and wraps up with the construction of a simple processor with support for a subset of the RISC-V ISA, using a single-cycle and a multi-cycle implementation approach.
The course lectures are accompanied by lab sessions that guide the student through an incremental design of a fully functional single-cycle processor data path. All design steps are synthesized into the FPGA of a TUL PYNQ-Z2, an integrated system-on-chip based on an ARM processor.
|
|
|
