Zhongliang ChenPh.D. Candidate, Dept. of ECE
Office: Room R306, 140 The Fenway
Email: zhonchen "at" ece "dot" neu "dot" edu
I am a PhD candidate at Department of Electrical and Computer Engineering, Northeastern University. My advisor is Dr. David Kaeli. I am a member of Northeastern University Computer Architecture Research Group (NUCAR). I received my master's degree in Computer Science from State Key Laboratory of Computer Architecture, Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) in 2010, and bachelor's degree in Information Engineering from School of Information and Communication Engineering, Beijing University of Posts and Telecommunications (BUPT) in 2007.
My research interests include parallel computing with Graphics Processing Units (GPU) and computer architecture. Currently, I am working on identifying and analyzing compiler- and architecture-level scalar opportunities in GPGPU applications. These opportunities are later utilized on the novel scalar-vector GPU architecture to improve performance and power efficiency. Also, I have abundant experience in GPU porting, profiling and optimizations.
During my master's career, I have done intensive research on microprocessor reliability at Reliable Design Research Group.
I worked as a GPU Architecture Intern in Advanced Processor Lab at Samsung Research America from May to August 2014. I was working on modeling and implementation of a complete tessellation pipeline, including hull shader, tessellator, and domain shader.
I worked as a Performance Compiler Engineer Intern at AMD Shader Compiler Group from July to December 2011. My work was primarily focused on compile-time scalar opportunity analysis in GPGPU applications and performance evaluation of scalar coprocessors in AMD Southern Islands GPUs.
In Spring 2011, I assisted Professor Kaeli to organize a GPU seminar for undergraduate students at Northeastern University.