Zhaoyang Han

I am Zhaoyang Han, a PhD candidate at Northeastern University advised by Prof. Miriam Leeser . I received my Bachelor's degree at University of Manchester and Master's degree at University of Pennsylvania. I mainly focus on reconfigurable hardwares and networking systems.

Contact: zhhan at(symbol) dot coe dot neu dot edu

Publications

EdgeQAT: Entropy and Distribution Guided Quantization-Aware Training for the Acceleration of Lightweight LLMs on the Edge

(Preprint)

Xuan Shen, Zhenglun Kong, Changdi Yang, Zhaoyang Han, Lei Lu, Peiyan Dong, Cheng Lyu, Chih-hsiang Li, Xuehang Guo, Zhihao Shu, Wei Niu, Miriam Leeser, Pu Zhao, Yanzhi Wang
arXiv preprint , 2024

P4-based In-Network Telemetry for FPGAs in the Open Cloud Testbed and FABRIC

(To Appear)

Sandeep Bal, Zhaoyang Han, Suranga Handagala; Mert Crevik, Michael Zink; Miriam Leeser
IEEE INFOCOM 2024-IEEE Conference on Computer Communications Workshops (INFOCOM WKSHPS) , 2024

A Framework to Enable Runtime Programmable P4-enabled FPGAs in the Open Cloud Testbed

(Best paper award)

Zhaoyang Han, Suranga Handagala; Kalyani Patle; Michael Zink; Miriam Leeser
IEEE INFOCOM 2023-IEEE Conference on Computer Communications Workshops (INFOCOM WKSHPS) , 2023

Hardware Software Codesign of Applications on the Edge: Accelerating Digital PreDistortion for Wireless Communications

Zhaoyang Han, Yiyue Jiang, Mushini Rahul, John Dooley, Miriam Leeser
2022 IEEE High Performance Extreme Computing Conference (HPEC'22) , 2022

Computationally Efficient Look-up-Tables for Behavioral Modelling and Digital Pre-distortion of Multi-Standard Wireless System

Zhaoyang Han, Meabh Loughman, Yiyue Jiang, Mushini Rahul, John Dooley, Miriam Leeser
16th EAI International Conference on Cognitive Radio Oriented Wireless Networks (EAI CROWNCOM'21) , 2021

Flightplan: Dataplane Disaggregation and Placement for P4 Programs

Nik Sultana, John Sonchack, Hans Giesen, Isaac Pedisich, Zhaoyang Han, Nishanth Shyamkumar, Shivani Burad, André DeHon, Boon Thau Loo
18th USENIX Symposium on Networked Systems Design and Implementation (NSDI'21) , 2021

Reducing FPGA compile time with separate compilation for FPGA building blocks

Yuanlong Xiao, Dongjoon Park, Andrew Butt, Hans Giesen, Zhaoyang Han, Rui Ding, Nevo Magnezi, Raphael Rubin, André DeHon
International Conference on Field-Programmable Technology (FPT'19) , 2019